Maximal clock division ratio, controls the width of the division counter.Ĭontrol clock, used for sampling control information. Optional features are available through different downloadable filesġ year support and customization service. Single divclk output that can serve as the clock source for block logic.Īsynchronous active low reset, care must be taken for proper reset separation and ordering when using this divider in a synchronous reset block. Synchronization of divratio, so Controlclk can be asynchronous to refclk Separate controlclk for sampling the divratio information, provides flexibility in clock scheme and timing closure. The dividers are used for generating lower frequency clocks from a faster reference clock.ĭivides with all natural power of 2 ratios up to the MAXRATIOĬan be connected to a constant divratio if necessary. This component contains RTL Verilog code for clock dividers based on counters. Using the same concept, a counter based clock divider can divide a clock by 2, 4, 8, etc. The simplest clock divider divides a clock frequency by 2 using a single flop and an inverter. Clock dividers generate slower clocks from a faster reference clock.
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